1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and in particular, to a double-diffused metal oxide semiconductor (DMOS) transistor and a fabricating method thereof, which can reduce on-resistance (Rds) by decreasing chip size.
2. Description of the Related Art
Semiconductor technology has recently been moving toward integrating power devices such as DMOS transistors, IGFETs (Insulated Gate Field Effect Transistors), and the like on a chip in a high density. These power devices, finding their wide use as individual devices and power ICs (Integrated Circuits), have channels formed by double-diffusion.
In particular, a DMOS transistor, obtained by double-diffusion, has impurity regions of different conductive types formed by sequentially diffusing impurities of different conductive types through a hole in an insulating layer. The double-diffusion structure of the DMOS transistor enables a short channel to be formed with high precision and the DMOS transistor to operate at high speed. DMOS transistors are grouped into vertical DMOS (VDMOS) transistors and lateral DMOS (LDMOS) transistors according to their current paths.
FIG. 1 is a sectional view of a conventional N-channel DMOS transistor. Referring to FIG. 1, an N+ buried layer 12 is formed on a P-type semiconductor substrate 10, and an N-type epitaxial layer 14 is formed over the substrate 10 and the N+ buried layer 12. A device isolation region 17 is formed over the N-type epitaxial layer 14, and an N+ sink region 16 is formed under a drain contact forming area by diffusing an N-type impurity of high concentration into the N+ buried layer 12.
A gate electrode 20 is formed over the N-type epitaxial layer 14 with a gate oxide film 18 formed between the two. A P-type body region 22 is formed into the surface of the N-type epitaxial layer 14, and an N+ source region 24 is formed to be surrounded by the P-type body region 22 in self-alignment with the gate electrode 20. An N+ drain region 26 is formed into the surface of the N-type epitaxial layer 14 in non-self-alignment with the gate electrode 20 from the outside thereof A channel region (not shown) is formed into the surface of the P-type body region 22 partially overlapped with the gate electrode 20.
An insulating layer 30 having a contact hole is formed over the N-type epitaxial layer 14 including the gate electrode 20. A metal layer 32 is formed in the contact hole of the insulating layer 30 to make contact with the gate electrode 20, the N+ source and drain regions 24 and 26, and the P-type body region 22 in the DMOS transistor.
In the conventional DMOS transistor as constituted above, a bulk bias region 28 should be formed to simultaneously make contact between the metal layer 32 and the N+ source region 24 and between the metal layer 32 and the P-type body region 22. In this way, the entire chip size is increased, in turn, increasing on-resistance.